Search - RAM vhdl

[Other Embeded program] DDram

Description: 07全国大学生电子设计竞赛C题获奖作品FPGA外围接口双口RAM部分源码-07 National Undergraduate Electronic Design Contest winning entries C title peripheral interface FPGA dual-port RAM part of source
Platform: | Size: 1024 | Author: SRY | Hits:

[Other] MEALY

Description: MEALY状态机的输出是现态和输入的函数.在SRAM控制器状态机中,写有效WE不仅和WRITE状态有关,还和总线命令WRITE_MASK有关.这样,输出WE信号按设计要求表示为现态WRITE和现态输入WRITE_MASK的函数.本程序基于VHDL,开发环境为MAXPLUS2-Mealy state machine output is now a function of state and input. In the SRAM controller state machine, the writing is not only effective WE and WRITE state, but also and bus-related WRITE_MASK command. In this way, WE output signal according to design requirements that the current state WRITE and is a function of state input WRITE_MASK. This procedure based on VHDL, development environment for MAXPLUS2
Platform: | Size: 29696 | Author: weixiaoyu | Hits:

[VHDL-FPGA-Verilog] acordwithram

Description: 一个牛人写的很快且不用状态机的动态RAM接口,VHDL编写-A cow were to write quickly and do not have the state machine dynamic RAM interface, VHDL prepared
Platform: | Size: 6144 | Author: john | Hits:

[VHDL-FPGA-Verilog] SDRAMconntrol

Description: SDRAM控制器的设计与VHDL实现是pdf格式的。在工程中实现过-SDRAM Controller Design with VHDL realize is pdf format. In the projects implemented
Platform: | Size: 138240 | Author: hjx | Hits:

[VHDL-FPGA-Verilog] VHDL_Programming_Examples

Description: vhdl例程,给出了许多VHDL例程,有参考价值,个人认为-VHDL routines, given a number of VHDL routines, there is reference value, individuals consider
Platform: | Size: 173056 | Author: 辜小兵 | Hits:

[VHDL-FPGA-Verilog] VHDL_Programming_Examples_2

Description: vhdl例程,给出了许多VHDL例程,有参考价值,个人认为，刚才上载的第2部分。-VHDL routines, given a number of VHDL routines, have reference value, personal opinion, just uploaded part 2.
Platform: | Size: 168960 | Author: 辜小兵 | Hits:

[VHDL-FPGA-Verilog] la_usb-SPISRAM

Description: 有关到SRAM的VHDL程序,也涉及到USB接口，希望对大家有所帮助-Related to the SRAM of the VHDL process involves the USB interface, and they hope to help everyone
Platform: | Size: 2048 | Author: 李锐 | Hits:

[VHDL-FPGA-Verilog] VHDL________

Description: VHDL programming samples WORD DOC FILE
Platform: | Size: 4096 | Author: kofway | Hits:

[Embeded-SCM Develop] fifov1

Description: FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。本FIFO的实现是利用双口RAM 和读写地址产生模块来实现的.FIFO的接口信号包括异步的写时钟（wr_clk）和读时钟（rd_clk）、与写时钟同步的写有效（wren）和写数据（wr_data）、与读时钟同步的读有效（rden）和读数据（rd_data）为了实现正确的读写和避免FIFO的上溢或下溢，给出与读时钟和写时钟分别同步的FIFO的空标志（empty）和满标志（full）以禁止读写操作。-FIFO (FIFO queue) is usually used for data caching and asynchronous signal used to accommodate the frequency or phase differences. The realization of this FIFO is to use dual-port RAM and to read and write address generator module achieved. FIFO interface signals, including asynchronous write clock (wr_clk) and read clock (rd_clk), and write effectively write clock synchronization (wren) and write data (wr_data), clock synchronization and time effective reading (rden) and read data (rd_data) in order to realize the right to read and write and to avoid FIFO overflow or the underflow, is given with the time clock and write clock synchronization FIFO respectively empty signs (empty) and full logo (full) to prohibit the read and write operations.
Platform: | Size: 378880 | Author: lsg | Hits:

[VHDL-FPGA-Verilog] ramlib_06

Description: 这是一个有关FIFO的VHDL 程序。。。请大家下载分享。-This is a FIFO of the VHDL program. . . Please download the U.S. share.
Platform: | Size: 577536 | Author: 张亚伟 | Hits:

[VHDL-FPGA-Verilog] sdram_ctrl.tar

Description: 同步动态RAM的控制电路VHDL源代码,在SOC开发中可以直接应用-Synchronous Dynamic RAM control circuit VHDL source code, in the SOC development can be applied directly
Platform: | Size: 90112 | Author: 26 | Hits:

[File Format] ram_da

Description: 将AD转换得到的八位数据存入RAM，存1000个点，然后通过串行DA读出，DA芯片为TLV5638,AD芯片为tlc0820ac，RAM为FM25L16-AD conversion will be the eight data into RAM, keep 1000 points, and then read out through the DA serial, DA chips for the TLV5638, AD chips for tlc0820ac, RAM for FM25L16
Platform: | Size: 650240 | Author: 王力 | Hits:

[VHDL-FPGA-Verilog] memio

Description: 最新VHDL 模块，实现对SRAM的控制，能直接用在ALTEAR XILLIX 等 FPGA上，-Latest VHDL modules to realize the control of SRAM can be directly used for ALTEAR XILLIX such as FPGA, the
Platform: | Size: 7168 | Author: 骑士 | Hits:

[VHDL-FPGA-Verilog] mif

Description: 编制FPGA中RAM所需要的MIF文件编制FPGA中RAM所需要的MIF文件-FPGA in the preparation of RAM required for the preparation of MIF files in the RAM of the FPGA needs MIF file
Platform: | Size: 1936384 | Author: 史东升 | Hits:

[VHDL-FPGA-Verilog] 32×4bitRAM

Description: 32×4bit 的RAM设计。VHD语言。能在ISE上仿真。-32 × 4bit the RAM design. VHD language. The simulation in ISE.
Platform: | Size: 3072 | Author: 张军 | Hits:

[Embeded-SCM Develop] testram_1

Description: EDA实验--RAM实验:利用-MegaWizard Plug-In Manager创建一个16×8的RAM，通过编程对RAM进行读写并在显示器上显示。本例使用三个按键PSW3，PSW2，PSW1，分别对应顶层文件中的x，y，we，we＝1对RAM写，xy＝11时，写入10101011；当xy＝01时，写入01010101；当xy＝10时，写入10101010。we＝0时，对RAM读出。三个按键按下时为0，当PSW1健按下时对RAM进行读出。 -EDA Experimental RAM experiment: the use-MegaWizard Plug-In Manager to create a 16 × 8 of the RAM, through the programming of the RAM read and write and displayed on the monitor. This example uses three buttons PSW3, PSW2, PSW1, corresponding to top-level document x, y, we, we = 1 on RAM write, xy = 11, the write 10101011 when xy = 01 hours, write 01010101 when xy = 10, the write 10101010. we = 0 when read out of RAM. Press the three keys for 0, when PSW1 Kin-pressed to read out of RAM.
Platform: | Size: 4096 | Author: 黄龙 | Hits:

[Other] ddr_ctrlv

Description: ddr ram controller vhdl code
Platform: | Size: 55296 | Author: heyong | Hits:

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